1. Field of the Invention
The present invention relates to a method of fabricating a metal programmable integrated circuit, and more specifically, to a method of fabricating an integrated circuit through utilizing metal layers to program randomly positioned basic units.
2. Description of the Prior Art
FIG. 1 is a diagram showing a prior art semiconductor body 10 of an integrated circuit. The semiconductor body has a plurality of functional circuit cells 12. The functional circuit cells 12 are arranged row-by-row or column-by-column according to an array format to finally form a matrix format. It is well-known that the matrix format corresponds to a minimum chip size. That is, the allocation of the functional circuit cells 12 corresponds to a maximum component density.
The semiconductor body 10 is divided into synchronous regions 14a, 14b and a non-synchronous region 16. All of the functional circuit cells 18a, 18b within the synchronous regions 14a, 14b operate according to a clock signal. For example, each of the functional circuit cells 18a, 18b respectively functions as a flip-flop, a latch, or a clock buffer after being defined by a corresponding routing design. On the other hand, the functional circuit cells 20 within the non-synchronous region 16 are not driven by clock signals.
Each functional circuit cell 20 is capable of performing a predetermined logic operation after being defined by a corresponding routing design. For example, each of the functional circuit cells 20 respectively functions as an AND logic gate circuit, an OR logic gate circuit, or an XOR logic gate circuit. After the integrated circuit designer hands over the designed photomask patterns to the maker of the semiconductor body 10, upper metal layers are then formed on the semiconductor body 10 based on the photomask patterns.
Please refer to FIG. 1 in conjunction with FIG. 2. FIG. 2 is a diagram showing traces routed within the synchronous regions 14a, 14b. In the synchronous region 14a, a clock trace 22a vertically crosses each functional circuit cell 18a of the synchronous region 14a. In addition, two power traces 24a, 26a also cross each functional circuit cell 18a of the synchronous region 14a. The power traces 24a, 26a are respectively used to provide operating voltages (a high voltage level Vdd and a low voltage level Vss for example) required by each functional circuit cell 18a. Similarly, a clock trace 22b and two power traces 24b, 26b vertically cross each functional circuit cell 18b of the synchronous region 14b. As shown in FIG. 2, power traces 24a, 24b, 26a, 26b are respectively located at both sides of the clock traces 22a, 22b so that noise transmitted by the clock traces 22a, 22b interfering with the clock signals is reduced. In other words, clock skew related to the clock signal is lessened.
As mentioned above, the semiconductor body 10 of the prior art integrated circuit is divided into synchronous regions 14a, 14b and a non-synchronous region 16. The functional circuit cells 18a, 18b, driven by the clock signals, are distributed in the synchronous regions 14a, 14b. That is, the prior art has to consider clock balance for controlling clock skew according to the geometric distribution of the synchronous regions 14a, 14b within the semiconductor body 10. However, based on the prior art, the semiconductor body 10 is required to define the synchronous regions 14a, 14b and the non-synchronous region 16. Therefore, when programming the semiconductor body 10 to perform a predetermined logic operation, the IC designer needs to consider the allocation of the synchronous regions 14a, 14b and the non-synchronous region 16 on the semiconductor body 10. It is obvious that the allocation of the synchronous regions 14a, 14b and the non-synchronous region 16 on the prior art semi-conductor body 10 is fixed. Therefore, it is impossible to elastically program traces routed among the transistors within the synchronous regions 14a, 14b and the non-synchronous region 16 for implementing another predetermined logic operation mentioned above.
Because the synchronous regions 14a, 14b and the non-synchronous region 16 on the semiconductor body 10 are defined according to a predetermined ratio, say, the ratio of transistors within the synchronous regions 14a, 14b to the transistors within the non-synchronous region 16, for respectively establishing the clocked logic circuits and the non-clocked logic circuits, the application field of the semiconductor body 10 is limited by the fixed allocation of the synchronous regions 14a, 14b and the non-synchronous region 16. That is, the application elasticity of the prior art semiconductor body 10 is bad.